
# For CVP13 Only! DDR4 UDIMM 64-bit, rank 1.

# Enable bitstream compression
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

set_property -dict {PACKAGE_PIN BB14 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports C0_DDR4_0_reset_n]

set_property -dict {PACKAGE_PIN AW16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_ba[0]]
set_property -dict {PACKAGE_PIN AY16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_ba[1]]
set_property -dict {PACKAGE_PIN BB17 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_bg[0]]
set_property -dict {PACKAGE_PIN BB16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_bg[1]]
set_property -dict {PACKAGE_PIN BB15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_cke[0]]
#set_property -dict {PACKAGE_PIN BC13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_cke[1]]
set_property -dict {PACKAGE_PIN BC12 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_odt[0]]
set_property -dict {PACKAGE_PIN BD11 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_cs_n[0]]
#set_property -dict {PACKAGE_PIN BA15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_cs_n[1]]
set_property -dict {PACKAGE_PIN AW18 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_ck_c[0]]
set_property -dict {PACKAGE_PIN AV18 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_ck_t[0]]
             
set_property -dict {PACKAGE_PIN BC16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_act_n]
set_property -dict {PACKAGE_PIN AT18 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[0]]
set_property -dict {PACKAGE_PIN AT17 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[1]]
set_property -dict {PACKAGE_PIN AU17 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[2]]
set_property -dict {PACKAGE_PIN AU16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[3]]
set_property -dict {PACKAGE_PIN AV17 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[4]]
set_property -dict {PACKAGE_PIN AV16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[5]]
set_property -dict {PACKAGE_PIN AR17 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[6]]
set_property -dict {PACKAGE_PIN AM17 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[7]]
set_property -dict {PACKAGE_PIN AM16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[8]]
set_property -dict {PACKAGE_PIN AP18 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[9]]
set_property -dict {PACKAGE_PIN AR18 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[10]]
set_property -dict {PACKAGE_PIN AL17 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[11]]
set_property -dict {PACKAGE_PIN AL16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[12]]
set_property -dict {PACKAGE_PIN AL15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[13]]
set_property -dict {PACKAGE_PIN AM15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[14]]
set_property -dict {PACKAGE_PIN AN17 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[15]]
set_property -dict {PACKAGE_PIN AN16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[16]]
#set_property -dict {PACKAGE_PIN AN18 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C0_DDR4_0_adr[17]]

set_property -dict {PACKAGE_PIN AR13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[0]]
set_property -dict {PACKAGE_PIN AP13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[1]]
set_property -dict {PACKAGE_PIN AN13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[2]]
set_property -dict {PACKAGE_PIN AM13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[3]]
set_property -dict {PACKAGE_PIN AM14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[4]]
set_property -dict {PACKAGE_PIN AL14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[5]]
set_property -dict {PACKAGE_PIN AT15 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[6]]
set_property -dict {PACKAGE_PIN AR15 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[7]]
set_property -dict {PACKAGE_PIN AW13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[8]]
set_property -dict {PACKAGE_PIN AW14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[9]]
set_property -dict {PACKAGE_PIN AV13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[10]]
set_property -dict {PACKAGE_PIN AU13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[11]]
set_property -dict {PACKAGE_PIN AV14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[12]]
set_property -dict {PACKAGE_PIN AU14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[13]]
set_property -dict {PACKAGE_PIN BA11 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[14]]
set_property -dict {PACKAGE_PIN AY11 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[15]]
set_property -dict {PACKAGE_PIN BB12 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[16]]
set_property -dict {PACKAGE_PIN BA12 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[17]]
set_property -dict {PACKAGE_PIN BA13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[18]]
set_property -dict {PACKAGE_PIN BA14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[19]]
set_property -dict {PACKAGE_PIN BA7  IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[20]]
set_property -dict {PACKAGE_PIN BA8  IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[21]]
set_property -dict {PACKAGE_PIN BC9  IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[22]]
set_property -dict {PACKAGE_PIN BB9  IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[23]]
set_property -dict {PACKAGE_PIN BD8  IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[24]]
set_property -dict {PACKAGE_PIN BD9  IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[25]]
set_property -dict {PACKAGE_PIN BD7  IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[26]]
set_property -dict {PACKAGE_PIN BC7  IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[27]]
set_property -dict {PACKAGE_PIN BF7  IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[28]]
set_property -dict {PACKAGE_PIN BE7  IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[29]]
set_property -dict {PACKAGE_PIN BE10 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[30]]
set_property -dict {PACKAGE_PIN BD10 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[31]]
set_property -dict {PACKAGE_PIN AN26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[32]]
set_property -dict {PACKAGE_PIN AM26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[33]]
set_property -dict {PACKAGE_PIN AR26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[34]]
set_property -dict {PACKAGE_PIN AR25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[35]]
set_property -dict {PACKAGE_PIN AP24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[36]]
set_property -dict {PACKAGE_PIN AP23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[37]]
set_property -dict {PACKAGE_PIN AM24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[38]]
set_property -dict {PACKAGE_PIN AL24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[39]]
set_property -dict {PACKAGE_PIN AU24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[40]]
set_property -dict {PACKAGE_PIN AT24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[41]]
set_property -dict {PACKAGE_PIN AV26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[42]]
set_property -dict {PACKAGE_PIN AU26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[43]]
set_property -dict {PACKAGE_PIN AU25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[44]]
set_property -dict {PACKAGE_PIN AT25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[45]]
set_property -dict {PACKAGE_PIN AV24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[46]]
set_property -dict {PACKAGE_PIN AV23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[47]]
set_property -dict {PACKAGE_PIN AW24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[48]]
set_property -dict {PACKAGE_PIN AW23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[49]]
set_property -dict {PACKAGE_PIN AY26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[50]]
set_property -dict {PACKAGE_PIN AY25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[51]]
set_property -dict {PACKAGE_PIN BB25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[52]]
set_property -dict {PACKAGE_PIN BB24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[53]]
set_property -dict {PACKAGE_PIN BA23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[54]]
set_property -dict {PACKAGE_PIN BA22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[55]]
set_property -dict {PACKAGE_PIN BE25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[56]]
set_property -dict {PACKAGE_PIN BD25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[57]]
set_property -dict {PACKAGE_PIN BF25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[58]]
set_property -dict {PACKAGE_PIN BF24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[59]]
set_property -dict {PACKAGE_PIN BF23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[60]]
set_property -dict {PACKAGE_PIN BE23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[61]]
set_property -dict {PACKAGE_PIN BD23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[62]]
set_property -dict {PACKAGE_PIN BC23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dq[63]]

set_property -dict {PACKAGE_PIN AT13 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_c[0]]
set_property -dict {PACKAGE_PIN AT14 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_t[0]]
set_property -dict {PACKAGE_PIN AY15 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_c[1]]
set_property -dict {PACKAGE_PIN AW15 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_t[1]]
set_property -dict {PACKAGE_PIN BB10 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_c[2]]
set_property -dict {PACKAGE_PIN BB11 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_t[2]]
set_property -dict {PACKAGE_PIN BF9  IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_c[3]]
set_property -dict {PACKAGE_PIN BF10 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_t[3]]
set_property -dict {PACKAGE_PIN AM25 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_c[4]]
set_property -dict {PACKAGE_PIN AL25 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_t[4]]
set_property -dict {PACKAGE_PIN AT23 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_c[5]]
set_property -dict {PACKAGE_PIN AR23 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_t[5]]
set_property -dict {PACKAGE_PIN AY23 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_c[6]]
set_property -dict {PACKAGE_PIN AY22 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_t[6]]
set_property -dict {PACKAGE_PIN BD24 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_c[7]]
set_property -dict {PACKAGE_PIN BC24 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dqs_t[7]]

set_property -dict {PACKAGE_PIN AN14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dm_n[0]]
set_property -dict {PACKAGE_PIN AY13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dm_n[1]]
set_property -dict {PACKAGE_PIN BA10 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dm_n[2]]
set_property -dict {PACKAGE_PIN BE8  IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dm_n[3]]
set_property -dict {PACKAGE_PIN AN23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dm_n[4]]
set_property -dict {PACKAGE_PIN AW25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dm_n[5]]
set_property -dict {PACKAGE_PIN BB22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dm_n[6]]
set_property -dict {PACKAGE_PIN BE22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C0_DDR4_0_dm_n[7]]

set_property -dict {IOSTANDARD DIFF_SSTL12 ODT RTT_48 PACKAGE_PIN AY18} [get_ports dimm0_refclk_clk_p]
set_property -dict {IOSTANDARD DIFF_SSTL12} [get_ports dimm0_refclk_clk_n]

#PCIe x1
set_property -dict {PACKAGE_PIN AP26 IOSTANDARD LVCMOS12} [get_ports pcie_perstn]
set_property -dict {PACKAGE_PIN AT10} [get_ports pcie_refclk_clk_n]
set_property -dict {PACKAGE_PIN AT11} [get_ports pcie_refclk_clk_p]
create_clock -period 10.000 -name refclk_100 [get_ports pcie_refclk_clk_p]

